提出了一种高效、简捷的 MPEG- 4纹理压缩零树编码电路.此电路较好地解决了零树编码电路中存在的两个瓶颈问题 :父子结点的递归处理与大系数的跳过处理.此电路充分利用 MPEG- 4零树编码符号集的特点，消除了繁复的递归处理，使各结点的符号标注在一次扫描中完成.另外，此电路利用全新的 ZTR地址缓存器，简捷地寻址 ZTR/VZTR后代结点，较大地减少了对存储空间的要求，并简化了大系数的跳过处理.另外，还设计了大系数预处理电路，通过简捷的比特或操作和比特非与操作，保证各位平面的独立编码.该电路在 FPGA集成电路平台上进行了验证.随着 MPEG- 4国际图象压缩标准的推广，此电路作为独立的 IP核，可以广泛地应用于视像设备之中.对于速度要求更高的设备，并行结构有待设计.

A novel hardware architecture of zerotree coding is presented for MPEG 4 texture coding. Under the architecture, two bottlenecks in zerotree coding are handled. The recursive scans of parent and children coefficients are avoided, and the skips of the significant coefficients and their descendents are fulfilled easily. The label coefficient is implemented in one scan by exploiting the features of MPEG 4 zerotree symbol alphabet. A ZTR address buffer is designed to simplify skipping processing of significant coefficients, and to fasten the search for the descendent coefficients of ZTR/VZTR nodes. A preprocessing unit of significant coefficients is also proposed with bit or and bit not and logic circuits, which is essential for independent coding of individual bitplane. The architecture is tested in a platform with FPGA chips. With the application of MPEA 4, the design can be applied to various equipments as an independent IP core. A parallel structure needs to implement for applications with stricter time requirement.