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一种针对H264的高性能反变换结构

方 健, 郑 伟, 王 匡, 李炳博(浙江大学 信息与电子工程学系,杭州 310027)

摘 要
H264的整数变换存在8×8和4×4两种尺寸大小,这增加了硬件设计的复杂性。同时,高清视频应用要求解码器具有更强的处理能力。针对这两个问题,文章提出了一种高性能的反变换硬件实现结构。对于4×4整数反变换,重构一个8×8亚宏块的4个4×4块,从而使两种尺寸大小的整数反变换具有相同的结构。采用优化的数据存储和流水设计,行列反变换能够同时执行,处理一个8×8亚宏块平均只需要32个时钟周期。转置存储器采用一个32×32bits的双口SRAM和8组寄存器组实现,和以前的设计相比,可以节省537%的存储器面积。在108 MHz工作频率下,本文提出的硬件结构能够有效执行H264高清实时解码的反变换运算。
关键词
A High Performance Inverse Integer Transform Architecture for H264

FANG Jian, ZHENG Wei, WANG Kuang, LI Bingbo(Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027)

Abstract
There are two kinds of integer transform in H264,8×8 integer transform and 4×4 integer transform This makes hardware design more complex At the same time, more powerful decoder is required for high definition video application High performance hardware architecture is proposed for 2D inverse integer transform in H264 For 4×4 inverse integer transform, four 4×4 blocks in an 8×8 sub-macroblock was reconstructed Therefore, the 8×8 2D inverse integer transform and 4×4 2D inverse integer transform could have the same architecture With a new strategy of data storage and pipeline, inverse transform for column data and inverse transform for row data could perform at the same time On average, 32 clocks were needed for processing an 8×8 sub-macroblock The transpose memory was composed of a two-port 32×32bits SRAM and 8 groups of registers Compared with former design, the new architecture could reduce 537% area of transpose memory When clocked at 108 MHz, the proposed design can perform real-time inverse transform for high definition video decoder of H264
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