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一种高效的CABAC解码器硬件结构设计

徐美华1, 吴明2, 周杰1(1.上海大学机电工程与自动化学院,上海 200072;2.上海市电站自动化技术重点实验室,上海 200072)

摘 要
相对于其他熵编码而言,基于上下文的自适应二进制算术熵编码(CABAC)具有更大的数据压缩率,但由于其运算复杂,访问存储设备频繁,导致编/解码率较低。针对影响CABAC解码速度的“瓶颈”问题,提出了一种高效的CABAC解码器硬件结构,包括新的存储访问方式、优化的解码核心单元结构以及子解码器级联的方式。实验结果表明,该硬件结构可显著提高CABAC的解码效率。
关键词
A High performance Hardware Architecture of CABAC Decoder

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Abstract
Comparing to other entropy coding standard,CABAC(context adaptive binary arithmetic coding) has more significant enhancement in compression.However,its encoding/decoding efficiency is low due to calculation complexity and costs in memory access.To deal with the "bottleneck" problem in decoding process,the article proposes efficient hardware architecture for CABAC decoder,including a new memory access mode,an optimizing decoding core and four concatenating decoding engines.The experimental results show that the decoding efficiency is greatly increased by the hardware architecture.
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