为了快速地进行小波变换，提出了一种应用于JPEG2000的基于提升格式5／3，9／7统一的离散小波滤波单元；同时对于行列并行滤波，提出了一种控制机制，其在缓存5行的条件下，可完成高速行列并行滤波操作。该方法在保证精度条件下，可以取得较高的硬件利用率，且中间数据暂存空间需求低。然后在提升结构基础上，完成了硬件模块设计，并进行了仿真和FPGA实现。最后用VerilogHDL对系统进行了硬件描述，并在AlteraDE2的验证板上的cyclone2EP2C35FC672芯片上，在Quartus6．0环境下实现了该结构功能。

A uniform 9/7 and 5/3 DWT filter by lifting scheme is proposed for JPEG2000. This paper also proposes a control method of row and column parallel filtering with minimum five lines cache. This architecture can achieve higher hardware utilization and lower temporary data storage without losing precision. By using this architecture, we have accomplished the hardware design. The algorithm is described by Verilog HDL, and simulated by modelsim, It is implemented by cyclone2-EP2C35FC672 under Altera DE2 board with Quartus 6. 0.