本文提出了适用于H.264/AVC宏块级反变换的IP核完整设计方案。首先，使用改进的T型结构同步宏块中的3种不同变换和反Zig Zag扫描。然后，对Hadamard反变换模块采用了时分复用存储器模块的设计方案，降低了系统时延；再利用IDCT矩阵运算可分离的特点，减少了IDCT模块资源消耗；最后，给出了以Xilinx Viretex2系列XC2V6000为目标器件的综合结果。仿真结果表明，该设计能够正确支持1080i 50Hz高清码流的实时解码。

A high throughput inverse transform IP core for H.264/AVC was proposed in this paper. The improved T architecture was presented to synchronize three different transforms and inverse ZigZag scan module. By applying time multiplexing buffer management to inverse Hadamard transform, we efficiently reduce its latency. Separability property of IDCT is also utilized to minimize its area. At last, the results of synthesis are given with Xilinx Virtex2 while XC2V6000 as the target device. The simulation performance shows that the design can effectively support the real time decoding of 1080i 50Hz HD stream.